New Functionality

1) Finvc compiles the SystemC part only when there are changes in the

interface between the Verilog part and the SystemC part of the

design.

2) finbuild includes the functionality of finbuildsc, which is not

available anymore.

3) Enhanced invocation option testing:

the $value$plusargs system function is supported.

Bug Fixes

1) Wires displayed with %d are now properly displyed. The bug was that

they were displayed in %b format.

7.0.4 Release date: 12/15/2005

7.0.0 Release date: 11/17/2005

6.2.09 Release date: 8/3/2005

6.2.06 Release date: 7/29/2005

6.2.05 Release date: 7/20/2005

6.1.04 Release date: 6/24/2005

6.1.02 Release date: 6/8/2005

6.1.1 Release date: 6/4/2005

6.1.0 Release date: 5/10/2005

6.0.12 Release date: 4/7/2005

6.0.11 Release date: 2/25/2005

6.0.10 Release date: 2/15/2005

6.0.09 Release date: 1/28/2005

6.0.08 Release date: 1/11/2005

6.0.07 Release date: 12/2/2004

6.0.06 Release date: 11/23/2004

6.0.05 Release date: 8/20/2004

6.0.04 Release date: 8/16/2004

6.0.03 Release date: 8/2/2004

6.0.02 Release date: 7/2/2004

6.0.01 Release date: 6/16/2004

6.0.00 Release date: 5/31/2004

5.0.24 Release date: 4/27/2004

5.0.23 Release date: 4/1/2004

5.0.22 Release date: 3/5/2004

5.0.21 Release date: 2/19/2004

5.0.20 Release date: 2/4/2004

5.0.19 Release date: 1/16/2004

5.0.18 Release date: 12/18/2003

5.0.17 Release date: 12/9/2003

5.0.16 Release date: 11/26/2003

5.0.15 Release date: 11/7/2003

5.0.14 Release date: 11/5/2003

5.0.13 Release date: 10/29/2003

5.0.12 Release date: 10/24/2003

5.0.11 Release date: 10/21/2003

5.0.10 Release date: 10/16/2003

5.0.09 Release date: 10/7/2003

5.0.08 Release date: 10/2/2003

5.0.07 Release date: 9/25/2003

5.0.06 Release date: 9/12/2003

5.0.05 Release date: 8/22/2003

5.0.04 Release date: 7/21/2003

5.0.03 Release date: 7/1/2003

5.0.02 Release date: 6/13/2003