Bug fixes for version 5_0_13

Updates for version 5_0_13

1) Implemented a faster algorithm for timing checks functions

2) The default is now not to use our proprietary virtual memory

mechanism for large Verilog memories. To enable use of virtual

memory, please add the option +fin_vmem to TOP.sim.

3) New option +fast_compile+++... to

facilitate lower compilation (finbuild) times for modules with

parameter overrides. May lead to higher simulation times.

4) Improved finvc performance.

5) Improved finbuild performance.