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Mixed SystemC/Verilog simlation modeling

SystemC modules instantiated in Verilog modules and

Verilog modules instantiated in SystemC.


This example runs on FinSim version 10_08_31 or higher.

It shows how one can instantiate Verilog modules in SystemC and SystemC modules in Verilog. In order to run this example one must execute the following commands:

finvc -systemc z2.cpp z2.v
finbuild
TOP.sim
The SystemC file, named here z2.cpp is listed below:

#include "systemc.h"

class vlog_lowlevel_scalar : public sc_foreign_module {
  public:
  sc_in  in;
  sc_out  out;
  vlog_lowlevel_scalar (sc_module_name nm) :
  sc_foreign_module(nm, "vlog_lowlevel_scalar"),
     in("in"),
     out("out")
  {}
};

class lowlevel_scalar : public sc_module {
public:
  sc_in in;
  sc_out out;

  SC_CTOR(lowlevel_scalar) : in("in"), out("out") {
    SC_METHOD(run);
    sensitive << in;

    vlog_lowlevel_scalar* vlog_lowlevel_scalar1;
    vlog_lowlevel_scalar1 = new vlog_lowlevel_scalar("vlog_lowlevel_scalar1");
    (*vlog_lowlevel_scalar1)(in, out);
  }
    ~lowlevel_scalar() {}

    void run() {
    }   
};

class model_scalar : public sc_module {
public:
  sc_in in;
  sc_out out;

  SC_CTOR(model_scalar) : in("in"), out("out") {
    SC_METHOD(run);
    sensitive << in;

    lowlevel_scalar* lowlevel_scalar1;
    lowlevel_scalar1 = new lowlevel_scalar("lowlevel_scalar1");
    (*lowlevel_scalar1)(in, out);
  }

  ~model_scalar() {}

  void run() {
    cout << "model_scalar: inst " << name() << " in = " << in.read() << "\n";
   }
};

class vlog_lowlevel_vector : public sc_foreign_module {
  public:
  sc_in  > in;
  sc_out  > out;
  vlog_lowlevel_vector (sc_module_name nm) :
  sc_foreign_module(nm, "vlog_lowlevel_vector"),
     in("in"),
     out("out")
  {}
};

class lowlevel_vector : public sc_module {
public:
  sc_in > in;
  sc_out > out;

  SC_CTOR(lowlevel_vector) : in("in"), out("out") {
    SC_METHOD(run);
    sensitive << in;

    vlog_lowlevel_vector* vlog_lowlevel_vector1;
    vlog_lowlevel_vector1 = new vlog_lowlevel_vector("vlog_lowlevel_vector1");
    (*vlog_lowlevel_vector1)(in, out);
  }
    ~lowlevel_vector() {}

    void run() {
    }   
};

class model_vector : public sc_module {
public:
  sc_in > in;
  sc_out > out;

  SC_CTOR(model_vector) : in("in"), out("out") {
    SC_METHOD(run);
    sensitive << in;

    lowlevel_vector* lowlevel_vector1;
    lowlevel_vector1 = new lowlevel_vector("lowlevel_vector1");
    (*lowlevel_vector1)(in, out);
  }

  ~model_vector() {}

  void run() {
    cout << "model_vector: inst " << name() << " in = " << in.read() << "\n";
   }
};

class vlog_lowlevel_2vectors : public sc_foreign_module {
  public:
  sc_in  > in1;
  sc_in  > in2;
  sc_out  > out1;
  sc_out  > out2;
  vlog_lowlevel_2vectors (sc_module_name nm) :
  sc_foreign_module(nm, "vlog_lowlevel_2vectors"),
     in1("in1"),
     in2("in2"),
     out1("out1"),
     out2("out2")
  {}
};

class lowlevel_2vectors : public sc_module {
public:
  sc_in > in1;
  sc_in > in2;
  sc_out > out1;
  sc_out > out2;

  sc_signal > inv_in2;

  SC_CTOR(lowlevel_2vectors) : in1("in1"), in2("in2"), out1("out1"), out2("out2") {
    SC_METHOD(run);
    sensitive << in2;

    vlog_lowlevel_2vectors* vlog_lowlevel_2vectors1;
    vlog_lowlevel_2vectors1 = new vlog_lowlevel_2vectors("vlog_lowlevel_2vectors1");
    (*vlog_lowlevel_2vectors1)(in1, inv_in2, out1, out2);
  }
  ~lowlevel_2vectors() {}

  void run() {
    inv_in2.write(~(in2.read()));
  }   
};

class model_2vectors : public sc_module {
public:
  sc_in > in1;
  sc_in > in2;
  sc_out > out1;
  sc_out > out2;

  SC_CTOR(model_2vectors) : in1("in1"), in2("in2"), out1("out1"), out2("out2") {
    SC_METHOD(run);
    sensitive << in1 << in2;

    lowlevel_2vectors* lowlevel_2vectors1;
    lowlevel_2vectors1 = new lowlevel_2vectors("lowlevel_2vectors1");
    (*lowlevel_2vectors1)(in1, in2, out1, out2);
  }

  ~model_2vectors() {}

  void run() {
    cout << "model_2vectors: inst " << name() << " in1 = " << in1.read() << " in2 = " << in2.read() << "\n";
   }
};

class vlog_lowlevel_large_vector : public sc_foreign_module {
  public:
  sc_in  > in;
  sc_out  > out;
  vlog_lowlevel_large_vector (sc_module_name nm) :
  sc_foreign_module(nm, "vlog_lowlevel_large_vector"),
     in("in"),
     out("out")
  {}
};

class lowlevel_large_vector : public sc_module {
public:
  sc_in > in;
  sc_out > out;

  SC_CTOR(lowlevel_large_vector) : in("in"), out("out") {
    SC_METHOD(run);
    sensitive << in;

    vlog_lowlevel_large_vector* vlog_lowlevel_large_vector1;
    vlog_lowlevel_large_vector1 = new vlog_lowlevel_large_vector("vlog_lowlevel_large_vector1");
    (*vlog_lowlevel_large_vector1)(in, out);
  }
    ~lowlevel_large_vector() {}

    void run() {
    }   
};

class model_large_vector : public sc_module {
public:
  sc_in > in;
  sc_out > out;

  SC_CTOR(model_large_vector) : in("in"), out("out") {
    SC_METHOD(run);
    sensitive << in;

    lowlevel_large_vector* lowlevel_large_vector1;
    lowlevel_large_vector1 = new lowlevel_large_vector("lowlevel_large_vector1");
    (*lowlevel_large_vector1)(in, out);
  }

  ~model_large_vector() {}

  void run() {
    //Too large to print.
    //cout << "model_large_vector: inst " << name() << " in = " << in.read() << "\n";
   }
};


The verilog code is located in the file z2.v and is listed below:
module top;
  reg ins1;
  wire outs1, ix_outs1;
  reg [0:66] inv1;
  reg [0:31] inv2;
  wire [0:66] outv1, ix_outv1;
  wire [0:31] outv2, ix_outv2;
  wire [66:0] inv3;
  wire [66:0] outv3, ix_outv3; 
  reg [0:79999] inlv1;
  wire [0:79999] outlv1, ix_outlv1;

  assign inv3 = inv1;

  initial begin
       #0;
       ins1 = 1'b0;
       inv1 = 67'b0000000000000000000000000000000000000000000000000000000000000000000;
       inv2 = 32'b00000000000000000000000000000000;
       inlv1 = 80000'b10zx10000000000000000000000000000;
       #10;
       ins1 = 1'b1;
       inv1 = 67'b1111111111111111111111111111111111111111111111111111111111111111111;
       inv2 = 32'b0000000000000000000000000000x0x1;
       inlv1 = 80000'b011001zzx10000000000000000000000;
       #10;
       ins1 = 1'bz;
       #10;
       inv1 = 67'b1z1z000000000000000000000000000000000000000000000000000000000000000;
       ins1 = 1'bx;
       #10;
       inv2 = 32'b00000000000000000000000000000000;
       ins1 = 1'b1;
       #10;
       inv1 = 67'b0000000000000000000000000000000000000000000000000000000000000001111;
       ins1 = 1'b0;
       #10;
       inv2 = 32'b00000000000000000000000000000x0x;
       #10;
       inv1 = 67'b1z1z000000000000000000000000000000000000000000000000000000000000000;
       #10 $finish;
 end

model_scalar       s1(ins1, outs1);
model_vector       v1(inv1, outv1);
model_2vectors     v2(~inv3, inv2, outv3, outv2);
model_large_vector l1(inlv1, outlv1);

model_ix ix1(ins1, inv1, inv2, inv3, inlv1, ix_outs1, ix_outv1, ix_outv2, ix_outv3, ix_outlv1);

initial $monitor("At %d:\n ins1 = %b\n outs1 = %b\n ix_outs1 = %b\n inv1 = %b\n outv1 = %b\n ix_outv1 = %b\n inv2 = %b\n outv2 = %b\n ix_outv2 = %b\n inv3 = %b\n outv3 = %b\n ix_outv3 = %b\n inlv1 = %b\n outlv1 = %b\n ix_outv1 = %b", 
$time, ins1, outs1, ix_outs1, inv1, outv1, ix_outv1, inv2, outv2, ix_outv2, inv3, outv3, ix_outv3, inlv1[79932:79999], outlv1[79932:79999], 
ix_outlv1[79932:79999]);
 
endmodule

module model_ix(ix_ins1, ix_inv1, ix_inv2, ix_inv3, ix_inlv1, ix_outs1, ix_outv1, ix_outv2, ix_outv3, ix_outlv1);
input ix_ins1;
output ix_outs1;
input [0:66] ix_inv1;
input [0:31] ix_inv2;
output  [0:66] ix_outv1;
output [0:31] ix_outv2;
input [66:0] ix_inv3;
output [66:0] ix_outv3;
input [0:79999] ix_inlv1;
output [0:79999] ix_outlv1;
   wire [0:66] 	 ix_inv1;
   wire [0:31] 	 ix_inv2;
   wire [0:66] 	 ix_outv1;
   wire [0:31] 	 ix_outv2;
   wire [66:0] 	 ix_inv3;
   wire [66:0] 	 ix_outv3;
   wire [0:79999] ix_inlv1;
   wire [0:79999] ix_outlv1;
   

model_scalar       ix_s1(ix_ins1, ix_outs1);
model_vector       ix_v1(ix_inv1, ix_outv1);
model_2vectors     ix_v2(ix_inv3, ix_inv2, ix_outv3, ix_outv2);
model_large_vector ix_l1(ix_inlv1, ix_outlv1);
  
endmodule

module model_scalar(in, out);
input in;
output out;
wire in;
wire out;
(* foreign = SystemC *)

endmodule

module model_vector(in, out);
input in;
output out;
wire [0:66] in;
wire [0:66] out;
(* foreign = SystemC *)

endmodule

module model_2vectors(in1, in2, out1, out2);
input in1;
input in2;
output out1;
output out2;
wire [0:66] in1;
wire [0:31] in2;
wire [0:66] out1;
wire [0:31] out2;
(* foreign = SystemC *)

endmodule


module model_large_vector(in, out);
input in;
output out;
wire [0:79999] in;
wire [0:79999] out;
(* foreign = SystemC *)

endmodule

module vlog_lowlevel_scalar(in, out);
input in;
output out;
wire in;
wire out;

assign out = in;
   
endmodule

module vlog_lowlevel_vector(in, out);
input in;
output out;
wire [0:66] in;
wire [0:66] out;

assign out = in;
   
endmodule

module vlog_lowlevel_2vectors(in1, in2, out1, out2);
input in1;
input in2;
output out1;
output out2;
wire [0:66] in1;
wire [0:31] in2;
wire [0:66] out1;
wire [0:31] out2;

assign out1 = in1;
assign out2 = in2;
   
endmodule

module vlog_lowlevel_large_vector(in, out);
input in;
output out;
wire [0:79999] in;
wire [0:79999] out;

assign out = in;

endmodule



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