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		Super-FinSim Super-FinSim is the top of the line FinSim Verilog simulator. Ever since the first FinSim Verilog simulator has been sold in 1993, the FinSim Verilog simulators have introduced many new features that have become state of the art in Verilog simulation: mixed Compiled and Interpreted simulation, simulation Farm that allows one engineer to manage hundreds of simultaneous simulations, separate and incremental compilation, high performance save and restart, direct integration with C code without the need for PLI, etc. Super FinSim supports the entire Verilog standard IEEE 1364-1995 and the features of IEEE 1364-2001, as listed in Support for Verilog 2001. It's support includes SDF, VCD, PLI, as well as excellent integration with other tools such as a tight integration via API (for better performance than PLI integration) with Debussy and Verdi debug environments from Novas Software, and excellent PLI integrations with Specman from Verisity and Vera from Synopsys for test benches, MMAV from Denali for memory models, Undertow from Veritools for debug environment, and others. In the DA Solution Limited `96 benchmark, the predecessor of Super-FinSim, FinSim-ECS, was rated the fastest Verilog simulator. FinSim was rated the fastest PC-based Verilog simulator in the ASIC & EDA benchmark. Super-FinSim runs on all popular platforms including Sun Solaris 32 and 64 bit, Linux 32 bit from all providers, Linux 64 bit from Madrake or SuSE, Windows NT/2000, Windows 95/98/ME, and XP. FinSim Developer FinSim Developer is an interpreted-only Verilog simulator. It supports the exact same features as Super FinSim with the exception of not providing compiled simulation and the absence of the ECS kernel for higher performance. In order to make Super FinSim behave exactly like FinSim Developer one must compile the verilog code using +fin_no_ecs -dsm int at the invocation of finvc (the Verilog compiler). FinSimMath simulation FinSimMath is an extension of Verilog for mathematical descriptions. FinSimMath supports: 1) changing formats (floating vs two's complement) and sizes of fields during the simulation based on a patent issued by the USPTO. 2) data containers of type real, cartesian and polar. 3) matrix operations (+, -, *, /, inversion, pseudo inversion, scalar product) 4) mixed scalar and matrix operations. 5) exception handling by providing an overflow signal associated to each variable precision data container. 6) numerous system tasks and functions as described in Chapter 8 of FinSim's User's Guide and as shown in the varous examples listed in finmath.html. 7) mixed FinSimMath and Verilog code in the same module and accross various modules. br>By bringing in the same language and the same simulation environment both the Mathematical level and the synthesizable Verilog RTL level of abstraction FinSimMath creates the possibility for increasing the productivity of designers implementing mathematical algorithms by a factor of over 1000, as was the case when Verilog and VHDL brought in the same language and same simualation environment the RTL and Gate levels of abstraction. One immediate advantage is that simulations can run over 1000 times faster by having them performed at the highest level (mathematical) where a 1 million point fft takes les than a second for most of the design and at the RTL for the smallest possible part, namely the part which is under inverstigation. Math2RTL Math2RTL translates FinSimMath descriptions into synthesizable, fully pipe-lined, Verilog RTL. Math2RTL requires a resource file in addition to the FinSimMath description in order to produce the synthesizable Verilog RTL. The resource file contains information about all resources used, such as adders, multipliers, etc. The information includes, type (real, cartesian, polar) format (floating or two's complement), sizes of fields, latency, operation to be performed, etc. Based on an option, Math2RTL produces high level models for all the resources used in the Verilog RTL implementing the given FinSimMath description. The same option includes in the code generated for the controller display statements and three include files provided by the user: name_launch_sim.inc, name_prepare_sim.inc, and name_display_results.inc in order to facilitate the simulation of mixed mathematical and RTL descriptions for various combinations of resources. FinCov FinCov is a high performance behavioral line coverage tool. Due to its tight integration with the simulation kernel, FinCov has a far smaller overhead and runs much faster than other code coverage tools, which use the PLI interface. It supports merging coverage results from different simulation runs. Site License Site licenses are available. For detailed information contact Alec Stanculescu at alec@fintronic.com. Components and number of lines limitation The component count is number of bi-directional switches + number of gates + number of primitives + number of continuous assignments + number of processes (initial + always) + number of module instantiations in the flattened design. To find out the exact number of components please use the option -verbose when running the simulator: TOP.sim  -verbose (for UNIX) or TOP.EXE -verbose (for Windows). Each limited version also has a limit on the number of lines in the source code. The limit is 3 x number of component limit, for example Super-FinSim 50K has a 50K component limitation and a 150K lines of Verilog source code  limitation. © Copyright 1999-2004, Fintronic USA, Inc.   All rights reserved.