Fintronic USA announces new pulse filtering techniques
San Mateo, CA (March 31, 1997)Fintronic USA, Inc. the supplier of high performance
Verilog driven simulators announces today that it has released, as scheduled, the new
pulse filtering techniques known as ``on-detect'', ``on-event'', and ``show-cancelled''.
The new techniques requested for ASIC signoff by AMI and LSI Logic, and discussed in EE
Times, provide a more conservative modeling solution to pulse filtering in Verilog HDL, by
extending the regions where the results are X. These techniques are proposed for IEEE
standardization within the 1364 Committee. ``By supporting the new pulse filtering
techniques Fintronic USA shows its continuous commitment for the enhancement of Verilog
HDL and for the IEEE Standardization effort in general'' said Dr Alec Stanculescu,
president of Fintronic USA. The new pulse filtering techniques are supported by all
Verilog Simulators developed by Fintronic USA, including by FinSim-ECS the Verilog
simulator that supports mixed cycle and event driven simulation.
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