What is new @ Fintronic ?

redball.gif (326 bytes)About Fintronic

redball.gif (326 bytes)What's new at Fintronic

redball.gif (326 bytes)What our customers are saying...

redball.gif (326 bytes)Support for Verilog 2001

redball.gif (326 bytes)Third party tools integrated with FinSim

home.htmlProductsSupportEvaluateContact



Fintronic extends Enhanced Cycle Simulation and introduces novel code coverage tool

Menlo Park, CA (May 21, 1996) Fintronic USA, Inc. which recently introduced the innovative Enhanced Cycle Simulation Technology (ECST) to its line of EDA products, announces today that it has successfully extended this ground-breaking technology to a wider class of Verilog designs for which the cycle simulation paradigm could not be used before. FinSim-ECS which supports the entire Verilog HDL consists of FinSim, a full fledged Verilog simulator and the ECS engine. FinSim-ECS automatically identifies the parts of the circuit that are suitable for simulation on the ECS engine and the rest is simulated by FinSim. Fintronic has improved the ECS engine so that modules with full timing specifications as well as some RTL-level modules can be now simulated by the ECS kernel without any change in the original Verilog code. Fintronic has specifically made a point out of testing its new technology on designs known in the industry for some time, such as the CMU and the DA Solutions benchmarks, in order to prove that this technology does not require a new design methodology.

``Our measurements show that by combining intelligent analysis of the designs with fast ECST, FinSim-ECS is able to achieve on some designs of the DA Solutions benchmark, speedups between 8 and 12 times over the performance of all Verilog software simulators reported upon in 1995 by DA Solutions. Of course, given a circuit designed to suit our cycle simulation paradigm, we would get 100 fold speedups, but the main point we want to emphasize is that this technology applies also to existing benchmarks, without any change in the designs`` says Dr Alec Stanculescu, president of Fintronic USA.

In addition, John Hillawi, Managing Director of DA Solutions mentions: ``The new release of FinSim-ECS has produced an overall speed up of x8-x12 and in one benchmark (Raynet) it has given as much as x100, without changing the design of the benchmark''.

Fintronic also continued to fulfill its commitment to improve the performance on the RTL-level designs by restructuring the front end of the simulator to increase the scope of existing optimizations and integrate them with more advanced ones. Thus, compared to FinSim 4.0 introduced at DAC 95, FinSim-ECS now shows up to three times speedups for the CMU benchmarks, the popular benchmarks for RTL-level.

Also today, Fintronic announces that it has added to its portfolio of EDA tools FinCov, a fast code coverage product which features a promising new technology. Whereas other code coverage tools are provided by third party vendors and interact with the simulation engine via the PLI interface, Fintronic's product is tightly integrated with FinSim's kernel allowing therefore for very fast data collection times. The users of FinCov will be able to run far more test vectors in the same amount of time it now takes them with PLI based code coverage tools. They will find out sooner which part of their design is redundant and will result in waste of silicon, which part has not been sufficiently tested or which part is over-tested consuming valuable simulation cycles.

The announcements today reaffirm Fintronic's strong commitment to provide the Verilog user community with accurate, powerful tools which will ultimately minimize the turnaround time of the design cycle and will substantially increase the productivity of our customers.

Platform support:

FinSim features the highest platform versatility in the industry by running on all popular platforms including UNIX for SUN, SGI, HP, DEC, Windows NT, Windows 3.1 and Windows 95, Linux and Sony NEWS.

Third Party Integration:

FinSim is tightly integrated with third party graphical environments such as SignalScan from Design Acceleration, Veribest from Veribest Inc., Ishizue from IK Technology, Undertow from Veritools, and ECS from Data I/O.

Pricing and Availability:

Fintronic USA's FinSim simulator featuring high performance Verilog Simulation is priced from $995 to $12,500 depending on product configuration and platform, and is available now. It is sold by Fintronic USA Inc., IK Technology, and Intergraph. FinSim-ECS which includes both FinSim and the ECS kernel has a list price between $20,000 and $25,000. The Verilog Analyzer from Fintronic USA, is currently part of products sold by Intergraph, Nextwave, ZyCAD, IST, IKT, and IKOS. FinCov will be available in Q3 1996. Fintronic has a Web page at http://www.fintronic.com, which can be used for placing orders, requesting demo licenses, checking prices, etc. Fintronic provides hotline support and software distribution via the Internet. For more information contact Dr Alec Stanculescu, president, at (650) 349 0108/x105 or e-mail him at alec@fintronic.com.

Mission:

Fintronic has a mission to supply the highest performance Verilog HDL simulators available for full language design verification and timing simulation. It is privately held and privately funded.

Acknowledgements:

Fintronic USA, Inc. acknowledges trademarks or registered trademarks of other organizations for their respective products and services.

For further information on the DA Solutions Benchmark Report, please contact DA Solutions at info@dasl.compulink.co.uk or telephone John Hillawi at +44 1705 365 473.

 


Copyright 1999-2011, Fintronic USA, Inc.   All rights reserved.