# FinSimMath FAQ

Copyright © Fintronic USA 2007. All rights reserved.

1.    What is FinSimMath?

FinSimMath is a natural extension of Verilog defining a special kind of register, syntax and semantic rules, and a set of functions and operators. The new kind of register holds integer, fixed point or floating point values, and its size as well as the sizes of its sub-fields can be changed dynamically. After every such change the new values assigned to the register will be governed by the new size and formats. Verilog code and FinSimMath code can be mixed without restrictions, and the special FinSimMath register inherits all properties of the Verilog reg construct.

FinSimMath includes also variable precision complex numbers with associated operations as well as matrix operations.

Overloading of operators including the assignment operator as well as internal support for numerous conversion functions eliminates the need for using explicit conversion functions which leads to a simple notation, so the use of FinSimMath is really easy to learn. Thit is especially true for those already familiar with the Verilog "quest for simplicity."

2.    What is unique about FinSimMath?

With FinSimMath extensions Verilog becomes the first HDL permitting design exploration during simulation (run time) in areas critical for arithmetic computations.

Another major FinSimMath advantage is that you can use standard Verilog in a natural way, because FinSimMath is an extension of Verilog, and you do not have to jump between two languages, one to analyze the system, and a second one to implement it. Designers get a perfect design exploration handle, without leaving their comfortable, and best known language for design.

3.    Is there a white paper on the variable precision capabilities which are included in FinSim?

At this time we do not have a separate white paper. However, this example
contains detailed information about the FinSimMath variable precision extensions, as well as a running examples showing the capabilities of FinSimMath in determining the optimal size of operands for a Butterworth IIR LP filter.

FinSim User's Guide 10.1
has Chapter 8 dedicated to FinSimMath.

4.    In what way does FinSimMath improve on what is available in commercial core generator tools?

Any methodology which uses a commercial core generator and tries to implement any optimization involving exploration via simulation as described in the literature would require the following:

1. some kind of analysis of simulation data
2. some external decision about a "move" or change of some kind
- sizes, rounding modes, normalization, or float to fixed

formats could be what is changed
3. changes have to be re-entered into the core generator
- one should not expect that all theoretical changes are

supported (some rounding modes and size choices might

not be available)
4. core is re-generated (new HDL is produced)
5. sizes of the adjacent modules have to be also changed
6. the system has to be tested for consistency
7. system is re-built (re-compiled, and re-elaborated)
8. sometimes stimulus vectors or test-benches have to be

adapted to new sizes too

Only after executing steps 2 to 8 one can expect to be able to go back to step 1 and repeat the cycle. For many reasons, this wide loop involving multiple tools and human intervention is not practical, and here is one of the areas where FinSimMath really helps (complementing what is available with current core generator tools).

Indeed, using FinSimMath, steps 1 to 8 above can be performed inside an elaborated design, meaning very fast, and this unprecedented combination of speed and capabilities is what enables a set of optimizations which were identified before [
Synthesis and Optimization of DSP Algorithms by George Constantinides et all] as “very desirable but not practical,” and a lot of new optimizations, like those aiming at power reduction.

All this is because in FinSimMath one can simply insert inside the

model (inside Verilog code) the whole optimization loop, implementing in Verilog the equivalent of the following algorithm

repeat
simulate design
if <trigger_condition> {change descriptor

for one or more variables}
until <optimality_condition_is_met>

Simulation continues to analyze behavior under new size(s), new

rounding(s), new normalization(s), or new format(s)....until some

optimality criteria condition is met.

This is a very tight loop indeed.

The trigger condition could be a statistical (cumulative over a group
of variables, over time, or over both) or a simultaneous condition (like an overflow). This way many optimization problems can be addressed.

5.    When will FinSi Math capabilities be available?

FinSimMath is available now. More exactly it is included in the FinSim release starting with release 9.0.

6.    What new applications and promising areas of investigation are opened by FinSimMath?

Applications involving one or more of the following phases are greatly simplified by FinSimMath

-         design of the golden floating point based model

-         design migration from floating point to fixed point

-         size optimization based on quantization noise criteria

-         fixed point scaling

-         estimating rounding effects

-         designs with custom floating point formats

-         optimal overflow avoidance

-         DSP design optimizations (including non-linear, or time variant)

-         low power optimizations and/or switching activity reduction

-         other tough optimization problems requiring early design exploration

Models of modern designs involving data-path re-configuration can be directly verified (simulated and analyzed) using FinSimMath Verilog extensions.

The ALU verification, and the design of specialized arithmetic units is also facilitated by the wide range support of FinSimMath.

The research race in finding best algorithms to change individual descriptors which bring convergence to useful cost functions while exploring a wide design space is now on. New techniques to design better bit margin functions could also be identified.

You are invited to develop new "in place algorithms", or experiment with previously non practical ones, while enjoying the other advantages of FinSimMath.

7.    Why are the FinSimMath capabilities feasible as extensions to discrete event languages like Verilog or SystemVerilog HDLs?

The HDLs require a run time invariance of the structure of the control-data-flow-graph (CDFG). Until FinSimMath the data could be changed only
through "flowing" it through some kind of conversion element. The
observation that flowing elements type themselves (as labels of the CDFG edges) could be changed without the need for global re-elaboration was critical for the design of FinSimMath. Indeed these changes do not alter the topology of the CDFG. FinSimMath adds numeric semantic to a specially identified Verilog register, therefore naturally extending Verilog and SystemVerilog.

8.    Why did these fixed and floating point capabilities not appear earlier in the standard HDLs (leaving a vacuum awkwardly filled by other, non event languages)?

Most probably, the designers of those HDLs were not aware of the fact that dynamic format changes were feasible at run time. The difficulty to support unbounded precision for a wide range of formats, and the implementation of scalable function libraries might have been the second reason. A third reason is that the ESL requirements including design exploration capabilities appeared after the specification phase of current standard HDLs was closed (for some more than five years ago) at a time when RTL and gates verification was the main priority.

9.    Can you compare FinSimMath capabilities to what will be available in VHDL 200X?

The VHDL packages which are planed to be added to the standard in the next revision cover signed, unsigned, fixed point, and floating point types. FinSimMath provides for all capabilities which will appear in VHDL, and have some extra advantages as:

1. Ability to change at run time sizes and formats associated to objects.
2. Ability to compute transcendental functions accurately and without the user’s guess for the number of iterations
3. Ability to handle different types of fixed and/or floating point in the same design
4. Ability to assign or manipulate values without the need to explicit type convert

These advantages are placing Verilog+FinSimMath ahead of any existing (or still to come) numeric solutions involving HDLs.

10.          What about using FinSimMath from within SystemVerilog?

Since SystemVerilog is in the main features a superset of Verilog, there is nothing to stop the usage of FinSimMath from within SystemVerilog. FinSim development team is currently evaluating the use of FinSimMath in conjunction with most popular SystemVerilog features.

11.          Will FinSimMath be available with other simulators?

Incorporating the FinSimMath capabilities into other simulators is feasible. Different levels of integration are available. Please contact Dr. Alec Stanculescu, alec@fintronic.com if interested in discussing more details.

12.          What are the plans for standardizing FinSimMath?

At this time there are no plans for a standardization path for FinSimMath.